Charge trap flash
Semiconductor memory using a silicon nitride charge trapping layer.
Wikipedia / Wikimedia Commons
Charge trap flash (CTF) is a semiconductor memory technology used to build non-volatile NOR and NAND flash memory. It belongs to the floating-gate MOSFET family but stores electrons in a silicon nitride film instead of the doped polycrystalline silicon used in conventional floating-gate designs. This difference lets manufacturers cut costs in five ways: fewer process steps to form the storage node, smaller process geometries (which shrink chip size and cost), the ability to store multiple bits per cell, better reliability, and higher yield because the charge trap is less vulnerable to point defects in the tunnel oxide layer.
The charge-trapping idea dates back to 1967, when John Szedon and Ting L. Chu first presented it. Later that year, a Sperry research team led by H.A. Richard Wegener invented the metal–nitride–oxide–semiconductor (MNOS) transistor, a MOSFET where the oxide layer is replaced by a double layer of nitride and oxide. Nitride served as a trapping layer instead of a floating gate, but the approach was considered inferior and saw limited use. Charge trap memory, introduced with MNOS devices in the late 1960s, stored charges in localized traps within a dielectric (typically silicon nitride), unlike floating-gate memory, which stores charges in a conducting material like doped polysilicon.
In 1974, charge trap technology was used as a storage mechanism in electrically erasable programmable read-only memory (EEPROM), offering an alternative to standard floating-gate MOSFET technology. By 1977, P.C.Y. Chen of Fairchild Camera and Instrument published a paper detailing SONOS, a MOSFET technology with much lower program and erase voltages and longer charge retention, leading to manufacturable charge-trapping EEPROMs in the 1980s.
Japanese NEC researchers—N. Kodama, K. Oyama, and Hiroki Shirai—developed a flash memory using a charge trap method in 1991. In 1998, Israeli engineer Boaz Eitan of Saifun Semiconductors patented NROM flash memory, which replaced the floating gate with a charge trapping layer. Two key innovations in that patent were localizing injected charges near the cell's drain and source terminals and using a reverse read concept to detect stored data at either end of the charge trap. These ideas enabled high cycling and, for the first time since the charge trapping concept was invented 30 years earlier, reliable charge trap flash pr
- field
- Semiconductor memory technology
- known_for
- Non-volatile NOR and NAND flash memory using a silicon nitride charge trapping layer
- first_high_volume_commercialization
- 2002 by AMD and Fujitsu
- market_share_2008
- 30% of $2.5 billion NOR flash market
Lore & Background
The charge-trapping concept was first presented by John Szedon and Ting L. Chu in 1967. In late 1967, a Sperry research team led by H.A. Richard Wegener invented the metal–nitride–oxide–semiconductor transistor (MNOS transistor), a type of MOSFET in which the oxide layer is replaced by a double layer of nitride and oxide. Nitride was used as a trapping layer instead of a floating gate, but its use was limited as it was considered inferior to a floating gate. Charge trap memory was introduced with MNOS devices in the late 1960s, storing charges in localized traps within a dielectric layer typically made of silicon nitride.
By 1974, charge trap technology was used as a storage mechanism in electrically erasable programmable read-only memory (EEPROM). In 1977, P.C.Y. Chen of Fairchild Camera and Instrument published a paper detailing the invention of SONOS, a MOSFET technology with far less demanding program and erase conditions and longer charge storage, leading to manufacturable EEPROM devices based on charge-trapping SONOS in the 1980s. In 1991, Japanese NEC researchers including N. Kodama, K. Oyama and Hiroki Shirai developed a type of flash memory that incorporated a charge trap method.
In 1998, Israeli engineer Boaz Eitan of Saifun Semiconductors patented a flash memory technology named NROM that took advantage of a charge trapping layer to replace the floating gate. Two important innovations appear in this patent: the localization of injected charges close to the cell's drain/source terminals, and utilizing a reverse read concept to detect stored data on either end of the charge trap. These ideas enabled high cycling and allowed reliable charge trap flash products to be produced for the first time since the charge trapping concept was invented 30 years earlier. In 2000, an AMD research team led by Richard M. Fastow, Khaled Z. Ahmed and Sameer Haddad demonstrated a charge trap mechanism for NOR flash memory cells.
Reader's Guide
Charge trap flash (CTF) represents a significant evolution in non-volatile memory technology, offering manufacturing cost advantages over conventional floating-gate flash. By using an insulating silicon nitride layer to trap electrons rather than a conductive polysilicon floating gate, CTF reduces process steps, allows smaller geometries, enables multiple bits per cell, improves reliability, and increases yield due to reduced susceptibility to point defects in the tunnel oxide layer. The technology was first commercialized in high volume in 2002 by AMD and Fujitsu with the GL NOR flash memory family, later produced under the Spansion name. By 2008, charge trapping flash accounted for 30% of the $2.5 billion NOR flash market. From the late 2000s, CTF became a core component of 3D V-NAND flash memory developed by Toshiba and Samsung Electronics. The key operational difference from floating gate is that the charge trapping layer is an insulator, making it relatively immune to short circuits caused by oxide defects; a short drains only electrons in immediate contact, leaving others in place. This allows a thinner tunnel oxide layer (50-70Å) compared to floating gate (~100Å), leading to faster program speed and lower tunneling voltages, which reduce stress on the tunnel oxide. The thin charge trapping layer also reduces capacitive coupling between neighboring cells, improving performance and scalability.
Did You Know?
- The charge-trapping concept was first presented by John Szedon and Ting L. Chu in 1967.
- In 1998, Israeli engineer Boaz Eitan of Saifun Semiconductors patented NROM, a flash memory technology using a charge trapping layer.
- Charge trapping flash accounted for 30% of 2008's $2.5 billion NOR flash market.
- From the late 2000s, CTF became a core component of 3D V-NAND flash memory developed by Toshiba and Samsung Electronics.
More in Egyptian inventions 1-24
Elsewhere in the Egyptian Inventions universe
Spotted an error? Know more?
This is a living reference — every entry is fact-audited, and reader corrections feed straight into our audit queue. Suggest an edit · See this site's audit record